1. Technical Field
The present invention generally relates to the field of solid-state memories, particularly to semiconductor memories and, even more particularly, to non-volatile semiconductor memories. Specifically, the invention relates to the class of non-volatile memories that are electrically programmable, i.e., the information content of which can be altered electrically.
2. Description of the Related Art
Non-volatile memory devices (shortly, non-volatile memories) are commonly used in several applications, when it is needed or desired that the data stored in the memory device are preserved even in absence of power supply.
Within the class of non-volatile memories, electrically alterable memories, particularly electrically programmable and erasable memories, such as Flash memories, have become very popular in those applications where the data to be stored are not immutable, being instead desirable from time to time to store new data, or to update the data previously stored (on the contrary, a consolidated microcode for a microprocessor is an example of data that are not expected to be changed).
Most electrically-programmable, non-volatile memories, like Flash memories, have memory cells formed of or including MOS transistors with a charge-storage element in the form of a floating-gate electrode, wherein to electric charges can be injected in order to vary a threshold voltage of the MOS transistor.
Typically, a semiconductor memory device includes a plurality of semiconductor memory cells, arranged for example in rows and columns so as to form a matrix of memory cells (“memory matrix”).
Depending on the way the memory cells in the memory matrix are interconnected, two classes of Flash memories can be identified: those having a so-called NOR architecture, or NOR Flash memories, and those having a so-called NAND architecture, shortly referred to as NAND Flash memories. Roughly speaking, in a NOR architecture the memory cells of a same matrix column are connected in parallel to a same bit line, whereas in a NAND architecture groups of memory cells of a same matrix column are serially interconnected so as to form respective strings (sometimes also referred to as “stacks”); several strings are connected, in parallel to each other, to a same bit line. Compared to NOR Flash memories, NAND Flash memories are more compact (a lower number of electrical contacts in the memory matrix), and they are also better suited for applications such as storage of files like digital images.
In memories having the NOR architecture, sense amplifiers are provided for sensing, i.e., reading the content of the memory cells, whereas program load circuits are used to program, i.e., write the information into the memory cells. Typically, eight or sixteen sense amplifiers, and as many program load circuits are provided in a memory, to enable sensing, and programming eight or sixteen memory cells in parallel.
In memories having the NAND architecture, the memory space is ideally partitioned into a plurality of memory pages, each page corresponding to a group of memory cells that, in operation, are accessed, i.e., read or written, simultaneously, i.e., in parallel to each other. The number of memory cells in each group determines the size (i.e., the number of bits) of the memory page. Memory pages of 8,192 (8K) cells are rather typical, but larger memory pages are also encountered, for example of 16,384 (16K) cells. A circuit arrangement referred to as “page buffer” is typically provided in a NAND flash memory for managing the operations of reading the information stored in the memory cells of a selected memory page, or altering the content of the memory page, particularly writing new information thereinto. In very general terms, the page buffer includes a buffer register wherein data read (in parallel) from the memory cells of a selected page are temporarily stored, before being serially outputted in chunks of, e.g., eight or sixteen bits, depending on the number of I/O terminals of the memory; similarly, when data are to be written into the memory, the page buffer is replenished with data received serially in said eight- or sixteen-bits chunks, and, after the page buffer has eventually been filled, the data are written in parallel into the memory cells of a selected memory page.
Memory devices are also classified based on the amount of information storable per memory cell. Memory devices capable of storing two bits of information per memory cell are referred to as “two-level” memories, whereas memory devices capable of storing more than just two information bits per memory cell are referred to as “multi-level” memories. Usually, the programming state of a memory cell is defined by the threshold voltage value of a MOS transistor included in the memory cell. In a two-level memory, each memory cell can be programmed in one of two distinct programming states, corresponding to two values (or values within two different ranges of values) of the threshold voltage of the MOS transistor of the memory cell. In particular, four-level memories are known, whose memory cells can be programmed in any one of four different programming states, each one associated with a corresponding logic value of the couple of bits they are adapted to store. In a memory cell adapted to store two bits, the threshold voltage values of the MOS transistor included in the generic memory cell may take one of four different values (or values within four different ranges of values).
Programming selected memory cells typically calls for applying to the memory cells to be programmed a sequence of programming pulses, wherein each programming pulse involves applying to the memory cells to be programmed predetermined biasing voltages (programming voltages) for a prescribed time. The data to be written into the memory cells (or corresponding data) are firstly latched into volatile latch elements provided in the program load circuits or in the page buffers; the latched data determine whether or not the memory cells have to receive the programming pulse.
Typically, after each programming pulse, the selected memory cells are read to assess whether they have reached the target programming state. As soon as a memory cell is verified as programmed to the target programming state, the information that was previously latched in the respective latch element (part of the program load circuits or of the page buffer) and that determined whether or not that cell should receive programming pulses is lost. The memory cell is applied no further programming pulses, and it is no longer subjected to any verify operation of its programming state: in other words, the successfully verified memory cell is permanently excluded from, i.e., it is permanently (as far as the considered program operation is concerned) prevented from being applied further programming pulses.